Computing architectures that integrate multiple diverse on-chip processing devices are becoming a dominant computing platform for many types of applications. A system that integrates more than one type of processor or core generally also includes certain memory that is shared between the processors or cores. For example, a last level cache (LLC) may be shared between multiple on-chip processing devices such as a central processing unit (CPU) and a graphics processing unit (GPU). An LLC is a critical resource because it can impact system performance. Designing a system with multiple diverse on-chip processing devices sharing a memory resource, however, can be complex due to conflicting requirements of the devices. For example, a common requirement in computing platforms to maximize resource utilization may be difficult to achieve when trying to minimize shared resource conflicts between a CPU and GPU. Thus, computer architectures that integrate multiple diverse on-chip processing devices could benefit from new solutions that manage conflicting requirements and characteristics of diverse on-chip processing devices.